1. Field of Invention
The present invention relates to a method for manufacturing a memory. More particularly, the present invention relates to a method for manufacturing a non-volatile memory.
2. Description of Related Art
Memory, so to speak, is a semiconductor device for storing data or information. When the function of a computer microprocessor becomes more powerful and the programs and computation of the software gets more complicated, the demand for the capacity of a memory increases accordingly. In order to satisfy the trend of the demand mentioned above, the technology and process to manufacture the inexpensive memory with high capacity has become the drive for manufacturing a high integrated device.
Among various memory products, non-volatile memory, having the ability for performing store, read, or erase data repeatedly and without loss of data after disconnection of power, has become a semiconductor device widely accepted by personal computer and electronic equipment.
FIGS. 1A through 1E are schematic diagrams showing a conventional method for manufacturing a non-volatile memory.
As shown in FIG. 1A, a substrate 100 having a trench isolation structure (not shown) for defining an active region is provided. A silicon oxide layer 102 is formed on the substrate 100. A first polysilicon layer 104 (poly 1) is formed on the silicon oxide layer 102. A silicon nitride layer 106 is formed on the first polysilicon layer 104.
As shown in FIG. 1B, a patterned photo resist layer (not shown) is formed on the silicon nitride layer 106. By using the patterned photo resist layer as an mask, the silicon nitride layer 106 is patterned to form a silicon nitride layer 106a. After the patterned photo resistance layer is removed, another process is performed to pattern the first polysilicon layer 104 to form a first polysilicon layer 104a by using the silicon nitride layer 106a as a mask.
As shown in FIG. 1C, by using the silicon nitride layer 106a as a mask, several source/drain region 108 are formed in the substrate 100. A chemical vapor deposition is performed to form a dielectric layer 110 over the substrate 100.
As shown in FIG. 1D, a planarization process is performed to remove a portion of the dielectric layer 110 to expose the top corner of the silicon nitride layer 106a. A process is performed to remove a portion of the dielectric layer 110 to form a dielectric layer 110a. The silicon nitride layer 106a is removed.
As shown in FIG. 1E, a second polysilicon layer 112 is formed over the substrate 100. The second polysilicon layer 112 (poly 3) orthogonally crosses the first polysilicon 104a and is served as a word line. Thereafter, the conventional processes for forming the non-volatile memory are performed. The details of the following processes are well know in the art and are not described hereafter.
However, in the convention method for manufacturing the non-volatile memory mentioned above, there exist problems described below. In the process for defining the first polysilicon layer 104, the polysilicon residual occurs due to the problem of that the etching process is uneasy to be controlled and the etching error happens. Therefore, the profile of the first polysilicon layer 104a is a taper profile indicated by an arrow labeled 113 in FIG. 1B. As a result, the bridge phenomenon happens between the later formed word lines (second polysilicon layer 112) so as to induce the leakage and decrease the reliability of the device.
Besides, the etching residual in dry etching process and the following wet process leads to the formation of the hole (indicated by an arrow labeled 116 in FIG. 1D) penetrating through the silicon oxide layer 102 due to the reaction between the etchant and the etching residual 114. Hence, while the second polysilicon layer 112 (word line) is formed over the substrate 100, the second polysilicon layer 112 fills into the hole 116 (as shown in FIG. 1D) and the second polysilicon layer 112 is abnormally electrically connected to the substrate 100 through the polysilicon material 118 (as shown in FIG. 1E) filling in the hole 116 (as shown in FIG. 1D). As a result, the device is invalid and the yield is decreased.